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ADS54J40 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS54J40 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 74 page  CLKIN 1.0 GSPS SYSREF ts_max ts_min Sample N ADS54J40 www.ti.com SBAS714A – MAY 2015 – REVISED OCTOBER 2015 6.8 Timing Characteristics Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted. MIN TYP MAX UNITS SAMPLE TIMING Aperture delay 0.75 1.6 ns Aperture delay matching between two channels on the same device ±70 ps Aperture delay matching between two devices at the same temperature and supply voltage ±270 ps Aperture jitter 145 fS rms WAKE-UP TIMING Wake-up time to valid data after coming out of global power-down 150 µs LATENCY Input Data latency(1): ADC sample to digital output 134 clock cycles Input OVR latency: ADC sample to OVR bit 62 clock cycles tPD Propagation delay: logic gates and output buffers delay (does not change with fS) 4 ns SYSREF TIMING tSU_SYSREF Setup time for SYSREF, referenced to the input clock falling edge 300 900 ps tH_SYSREF Hold time for SYSREF, referenced to the input clock falling edge 100 ps JESD OUTPUT INTERFACE TIMING CHARACTERISTICS Unit interval 100 400 ps Serial output data rate 2.5 10 Gbps Total jitter for BER of 1E-15 and lane rate = 10 Gbps 26 ps Random jitter for BER of 1E-15 and lane rate = 10 Gbps 0.75 ps rms Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps 12 ps, pk-pk Data rise time, data fall time: rise and fall times are measured from 20% to 80%, tR, tF 35 ps differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps (1) Overall ADC latency = data latency + tPDI. Figure 1. SYSREF Timing Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ADS54J40 |
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