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ADS9110IRGET Datasheet(PDF) 7 Page - Texas Instruments |
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ADS9110IRGET Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 62 page  ADS9110 www.ti.com SBAS629A – OCTOBER 2015 – REVISED OCTOBER 2015 6.6 Timing Requirements: Conversion Cycle All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted. All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 1. MIN TYP MAX UNIT TIMING REQUIREMENTS fcycle Sampling frequency 2 MHz tcycle ADC cycle time period 500 ns twh_CONVST Pulse duration: CONVST high 30 ns twl_CONVST Pulse duration: CONVST low 30 ns tacq Acquisition time 150 ns tqt_acq Quiet acquisition time(1) 25 ns td_cnvcap Quiet aperture time(1) 10 ns TIMING SPECIFICATIONS tconv Conversion time 300 340 ns (1) See Figure 48. 6.7 Timing Requirements: Asynchronous Reset, NAP, and PD All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted. All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 2 and Figure 3. MIN TYP MAX UNIT TIMING REQUIREMENTS twl_RST Pulse duration: RST low 100 ns TIMING SPECIFICATIONS td_rst Delay time: RST rising to RVS rising 1250 µs tnap_wkup Wake-up time: NAP mode 300 ns tPWRUP Power-up time: PD mode 250 µs 6.8 Timing Requirements: SPI-Compatible Serial Interface All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted. All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 4. MIN TYP MAX UNIT TIMING REQUIREMENTS fCLK Serial clock frequency 75 MHz tCLK Serial clock time period 13.33 ns tph_CK SCLK high time 0.45 0.55 tCLK tpl_CK SCLK low time 0.45 0.55 tCLK tsu_CSCK Setup time: CS falling to the first SCLK capture edge 5 ns tsu_CKDI Setup time: SDI data valid to the SCLK capture edge 1.2 ns tht_CKDI Hold time: SCLK capture edge to (previous) data valid on SDI 0.65 ns tht_CKCS Delay time: last SCLK falling to CS rising 5 ns TIMING SPECIFICATIONS tden_CSDO Delay time: CS falling to data enable 4.5 ns tdz_CSDO Delay time: CS rising to SDO going to 3-state 10 ns td_CKDO Delay time: SCLK launch edge to (next) data valid on SDO 6.5 ns td_CSRDY_f Delay time: CS falling to RVS falling 5 ns After NOP operation 10 Delay time: td_CSRDY_r ns CS rising to RVS rising After WR or RD operation 70 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: ADS9110 |
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