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DLPC3433ZVB Datasheet(PDF) 8 Page - Texas Instruments |
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DLPC3433ZVB Datasheet(HTML) 8 Page - Texas Instruments |
8 / 62 page DLPC3433, DLPC3438 DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016 www.ti.com Pin Functions – Parallel Port Input Data and Control(1)(2) PIN DESCRIPTION I/O NAME NUMBER PARALLEL RGB MODE BT656 INTERFACE MODE PCLK P3 I11 Pixel clock(3) Pixel clock(3) PDM_CVS_TE N4 B5 Parallel data mask(4) Unused(5) VSYNC_WE P1 I11 Vsync(6) Unused(5) HSYNC_CS N5 I11 Hsync(6) Unused(5) DATAEN_CMD P2 I11 Data Valid(6) Unused(5) (TYPICAL RGB 888) PDATA_0 K2 Blue (bit weight 1) BT656_Data (0) PDATA_1 K1 Blue (bit weight 2) BT656_Data (1) PDATA_2 L2 Blue (bit weight 4) BT656_Data (2) PDATA_3 L1 Blue (bit weight 8) BT656_Data (3) I11 PDATA_4 M2 Blue (bit weight 16) BT656_Data (4) PDATA_5 M1 Blue (bit weight 32) BT656_Data (5) PDATA_6 N2 Blue (bit weight 64) BT656_Data (6) PDATA_7 N1 Blue (bit weight 128) BT656_Data (7) (TYPICAL RGB 888) PDATA_8 R1 Green (bit weight 1) PDATA_9 R2 Green (bit weight 2) PDATA_10 R3 Green (bit weight 4) PDATA_11 P4 Green (bit weight 8) I11 Unused PDATA_12 R4 Green (bit weight 16) PDATA_13 P5 Green (bit weight 32) PDATA_14 R5 Green (bit weight 64) PDATA_15 P6 Green (bit weight 128) (TYPICAL RGB 888) PDATA_16 R6 Red (bit weight 1) PDATA_17 P7 Red (bit weight 2) PDATA_18 R7 Red (bit weight 4) PDATA_19 P8 Red (bit weight 8) I11 Unused PDATA_20 R8 Red (bit weight 16) PDATA_21 P9 Red (bit weight 32) PDATA_22 R9 Red (bit weight 64) PDATA_23 P10 Red (bit weight 128) 3D reference • For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the host when a 3D command is not provided. Must transition in the middle of each frame 3DR N6 (no closer than 1 ms to the active edge of VSYNC) • If a 3D application is not used, then this input should be pulled low through an external resistor. (1) PDATA(23:0) bus mapping is pixel format and source mode dependent. See later sections for details. (2) PDM_CVS_TE is optional for parallel interface operation. If unused, inputs should be grounded or pulled down to ground through an external resistor (8 k Ω or less). (3) Pixel clock capture edge is software programmable. (4) The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to ground through an external resistor (8 k Ω or less). (5) Unused inputs should be grounded or pulled down to ground through an external resistor (8 k Ω or less). (6) VSYNC, HSYNC, and DATAEN polarity is software programmable. 8 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLPC3433 DLPC3438 |
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