1

1

2

2

3

3

5

5

4

4

6

6

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 LSB+1

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D7

8

7

7

Previous Conversion Data

MSB

EOC

Initialize

Initialize

INT

A/D Conversion Interval

LSB

DATA OUT

I/O CLOCK

DATA IN

CS

t

conv

Low Level

Access Cycle

Sample Cycle

Shift in New Multiplexer Address,

Simultaneously Shift Out

Previous Conversion Result

Channel Address

Output Data

Format

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5 MSB–6

MSB

1

2

3

5

4

6

10

11

12

1

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

MSB–8 MSB–9 LSB+1

2

3

D6

D5

D4

D3

D2

D1

D0

D6

D5

D7

8

7

9

MSB–6 MSB–7

D7

Previous Conversion Data

MSB

MSB

MSB–2

MSB–1

A/D Conversion Interval

EOC

Initialize

Initialize

INT

LSB

DATA OUT

I/O CLOCK

DATA IN

CS

Hi-Z State

t

conv

Access Cycle

Sample Cycle

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Channel Address

Output Data

Format

TLV2556

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SLAS355B – DECEMBER 2001 – REVISED DECEMBER 2015

NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a set-up time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 3. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First

NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a set-up time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 4. Timing for 8-Clock Transfer Not Using CS With DATA OUT Set for MSB First

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