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TPL5100 Datasheet(PDF) 6 Page - Texas Instruments |
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TPL5100 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 20 page TPL5100 SNAS629C – JULY 2013 – REVISED DECEMBER 2014 www.ti.com 6.6 Timing Requirements TCAL, MOS_DRV, DONE, PGOOD MIN NOM MAX UNIT trTCAL Rise Time TCAL Capacitve load 15 pF 50 ns tfTCAL Fall Time TCAL Capacitve load 15 pF 50 ns trMOS_DRV Rise Time MOS_DRV Capacitve load 50 pF 4 ns tfMOS_DRV Fall Time MOS_DRV Capacitve load 50 pF 50 ns Min delay 100 ns tDDONE DONE to MOS_DRV delay Max delay tDP-5 × ms tCAL tDTCAL TCAL to MOS_DRV delay tCAL/2 ms Figure 1. Timing Diagram 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: TPL5100 |
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