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LAN8820I Datasheet(PDF) 4 Page - Microchip Technology |
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LAN8820I Datasheet(HTML) 4 Page - Microchip Technology |
4 / 83 page LAN8820/LAN8820I DS00001871B-page 4 2009-2015 Microchip Technology Inc. 1.0 INTRODUCTION The LAN8820/LAN8820i is a low-power 10BASE-T/100BASE-TX/1000BASE-T Gigabit Ethernet physical layer (PHY) transceiver that is fully compliant with the IEEE 802.3 and 802.3ab standards. The LAN8820/LAN8820i can be configured to communicate with an Ethernet MAC via the standard RGMII interface. It contains a full-duplex transceiver for 1000Mbps operation on four pairs of category 5 or better balanced twisted pair cable. Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V. The LAN8820/LAN8820i is configurable via hardware and software, supporting both IEEE 802.3-2005 compliant and vendor-specific register functions via SMI. The LAN8820/LAN8820i implements Auto-Negotiation to automatically determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct con- nect or cross-over cables. An internal block diagram of the LAN8820/LAN8820i is shown in Figure 1-1. A typical system-level diagram is shown in Figure 1-2. FIGURE 1-1: INTERNAL BLOCK DIAGRAM FIGURE 1-2: SYSTEM LEVEL BLOCK DIAGRAM LAN8820/LAN8820i RGMII 3 2 1 Active Hybrid 0 10/100/1000 Ethernet 3 2 1 Analog RX 0 3 2 1 Analog TX 0 3 2 1 DSP 0 3 2 1 Spectral Shaper 0 Digital TX Scrambler Trellis 4DPAM-5 Encoders Digital RX Descrambler Viterbi Decoder 4DPAM-5 Decoders 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Physical Coding Sublayer TAP Controller LEDs PLL LEDs JTAG 3 2 1 0 32 1 0 LAN8820/ LAN8820i 10/100/1000 Ethernet MAC LED Status RGMII Crystal MDI Ethernet Magnetics JTAG Ethernet |
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