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RPC56EL60L5BFQY Datasheet(PDF) 8 Page - STMicroelectronics |
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RPC56EL60L5BFQY Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 137 page Introduction RPC56EL60L5 8/137 DocID026934 Rev 1 Table 1. RPC56EL60L5 device summary Feature RPC56EL60 CPU Type 2 × e200z4 (in lock-step or decoupled operation) Architecture Harvard Execution speed 0–120 MHz (+2% FM) DMIPS intrinsic performance >240 MIPS SIMD (DSP + FPU) Yes MMU 16 entry Instruction set PPC Yes Instruction set VLE Yes Instruction cache 4 KB, EDC MPU-16 regions Yes, replicated module Semaphore unit (SEMA4) Yes Buses Core bus AHB, 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data Crossbar Master × slave ports Lock Step Mode: 4 × 3 Decoupled Parallel Mode: 6 × 3 Memory Flash 1 MB, ECC, RWW Static RAM (SRAM) 128 KB, ECC Modules Interrupt Controller (INTC) 16 interrupt levels, replicated module Periodic Interrupt Timer (PIT) 1 × 4 channels System Timer Module (STM) 1 × 4 channels, replicated module Software Watchdog Timer (SWT) Yes, replicated module eDMA 16 channels, replicated module FlexRay 1 × 64 message buffers, dual channel FlexCAN 2 × 32 message buffers LINFlexD (UART and LIN with DMA support) 2 Clock out Yes Fault Collection and Control Unit (FCCU) Yes Cross Triggering Unit (CTU) Yes eTimer 3 × 6 channels(1) FlexPWM 2 Module 4 × (2 + 1) channels(2) Analog-to-Digital Converter (ADC) 2 × 12-bit ADC, 16 channels per ADC (3 internal, 4 shared and 9 external) Sine Wave Generator (SWG) 32 point |
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