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DP83867CSRGZT Datasheet(PDF) 4 Page - Texas Instruments |
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DP83867CSRGZT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 114 page  DP83867CS, DP83867IS, DP83867E SNLS504 – OCTOBER 2015 www.ti.com Table 2. Pin Functions PIN TYPE(1) DESCRIPTION NAME NUMBER MAC INTERFACES (SGMII, RGMII) TRANSMIT DATA Bit 3: This signal carries data from the MAC to the PHY in TX_D3 25 I, PD RGMII mode. It is synchronous to the transmit clock GTX_CLK. TRANSMIT DATA Bit 2: This signal carries data from the MAC to the PHY in TX_D2 26 I, PD RGMII mode. It is synchronous to the transmit clock GTX_CLK. Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. SGMII_SIP 27 I, PD This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. TRANSMIT DATA Bit 1: This signal carries data from the MAC to the PHY in TX_D1 27 I, PD RGMII mode. It is synchronous to the transmit clock GTX_CLK. Differential SGMII Data Input: This signal carries data from the MAC to the PHY in SGMII mode. It is synchronous to the differential SGMII clock input. SGMII_SIN 28 I, PD This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. TRANSMIT DATA Bit 0: This signal carries data from the MAC to the PHY in TX_D0 28 I, PD RGMII mode. It is synchronous to the transmit clock GTX_CLK. RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the GTX_CLK 29 I, PD MAC layer to the PHY. Nominal frequency is 125 MHz. RGMII RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 2.5 MHz in 10 Mbps mode. RX_CLK 32 O 25 MHz in 100 Mbps mode. 125 MHz in 1000 Mbps mode. Differential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the PHY in SGMII mode. SGMII_COP 33 S, O This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. RECEIVE DATA Bit 0: This signal carries data from the PHY to the MAC in RX_D0 33 S, O, PD RGMII mode. It is synchronous to the receive clock RX_CLK. Differential SGMII Clock Output: This signal is a continuous 625MHz clock signal driven by the MAC in SGMII mode. SGMII_CON 34 S, O, PD This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. RECEIVE DATA Bit 1: This signal carries data from the PHY to the MAC in RX_D1 34 O, PD RGMII mode. It is synchronous to the receive clock RX_CLK. Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output. SGMII_SOP 35 S, O, PD This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. RECEIVE DATA Bit 2: This signal carries data from the PHY to the MAC in RX_D2 35 S, O, PD RGMII mode. It is synchronous to the receive clock RX_CLK. Differential SGMII Data Output: This signal carries data from the PHY to the MAC in SGMII mode. It is synchronous to the differential SGMII clock output. SGMII_SON 36 S, O, PD This pin should be AC coupled to the MAC via a 0.1µF capacitor when operating in SGMII mode. (1) The definitions below define the functionality of each pin. (a) Type: I Input (b) Type: O Output (c) Type: I/O Input/Output (d) Type: PD, PU Internal Pulldown/Pullup (e) Type: S Configuration Pin (f) Type: P Power or GND (g) Type: A Analog pins NOTE: Internal Pull-Up/Pull-Down resistors on the IO pins are disabled when the device enters functional mode after power up. 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated |
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