DS42MB100

SNLS244H – SEPTEMBER 2006 – REVISED JANUARY 2016

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Pin Functions (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND

RSV

17

I

through an external pull-down resistor.

POWER

2, 8, 9, 12,

Ground reference. Each ground pin should be connected to the ground plane through a low

GND

14, 16, 20,

P

inductance path, typically with a via located as close as possible to the landing pad of the GND

29, 35

pin.

DAP is the metal contact at the bottom side, located at the center of the WQFN package. It

GND

DAP

P

should be connected to the GND plane with at least 16 via to lower the ground impedance and

improve the thermal performance of the package.

5, 13, 15,

P

23, 32

It is recommended to have a 0.01

pin to ground plane.

6 Specifications

6.1 Absolute Maximum Ratings

see

(1) (2)

MIN

MAX

UNIT

–0.3

4

V

CMOS/TTL input voltage

–0.3

V

CML input/output voltage

–0.3

V

Junction temperature

150

°C

Lead temperature (soldering, 4 seconds)

260

°C

–65

150

°C

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), 1.5 k

Ω, 100 pF, per ANSI/ESDA/JEDEC JS-

±6000

Electrostatic discharge

V

±1250

Machine model

±350

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4

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