DS100MB203 datasheet(8/54 Pages) TI1

Part #	DS100MB203

Description	10.3125 Gbps Dual Lane 2:1/1:2 Mux/Buffer

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8

DS100MB203

SNLS396D – JANUARY 2012 – REVISED JANUARY 2016

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(1)

Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(2)

The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(3)

In GEN3 mode, the output VOD level is not fixed. It will be adjusted automatically based on the VID input amplitude level. The output

VOD level set by DEM_x[1:0] in GEN3 mode is dependent on the VID level and the frequency content. The DS100MB203 repeater in

GEN3 mode is designed to be transparent, so the TX-FIR (de-emphasis) is passed to the RX to support the PCIe GEN3 handshake

negotiation link training.

6.5 Electrical Characteristics

(1) (2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER

PD

Power dissipation

EQ Enabled, VOD = 1 Vp-p,

RESET = 0

VDD = 2.5-V supply

390

499

mW

VIN = 3.3-V supply

515

684

mW

LVCMOS / LVTTL DC SPECIFICATIONS

Vih

High-level input

voltage

2

VDD

V

Vil

Low-level input

voltage

0

0.8

V

Voh

High-level output

voltage (ALL_DONE

pin)

Ioh= −4mA

2

V

Vol

Low-level output

voltage (ALL_DONE

pin)

Iol= 4mA

0.4

V

Iih

Input high current

(RESET pin)

VIN = 3.6 V,

LVCMOS = 3.6 V

–15

15

µA

Input high current

with internal resistors

(4–level input pin)

VIN = 3.6 V,

LVCMOS = 3.6 V

20

150

µA

Iil

Input low current

(RESET pin)

VIN = 3.6 V,

LVCMOS = 0 V

–15

15

µA

Input low current with

internal resistors

(4–level input pin)

VIN = 3.6 V,

LVCMOS = 0 V

–160

–40

µA

CML RECEIVER INPUTS (IN_n+, IN_n–)

RLrx-diff

RX differential return

loss

0.05 - 1.25 GHz

–16

dB

1.25 - 2.5 GHz

–16

dB

2.5 - 4.0 GHz

–14

dB

RLrx-cm

RX common-mode

return loss

0.05 - 2.5 GHz

–12

dB

2.5 - 4.0 GHz

–8

dB

Zrx-dc

RX DC common-

mode impedance

Tested at VDD = 2.5 V

40

50

60

Ω

Zrx-diff-dc

RX DC differntial

mode impedance

Tested at VDD = 2.5 V

80

100

120

Ω

Vrx-signal-det-

diff-pp

Signal detect assert

level for active data

signal

0101 pattern at 8 Gbps

180

mVp-p

Vrx-idle-det-diff-

pp

Signal detect de-

assert level for

electrical idle

0101 pattern at 8 Gbps

110

mVp-p

HIGH-SPEED OUTPUTS

Vtx-diff-pp

Output voltage

differential swing

Differential measurement with OUT_n+ and OUT_n-,

terminated by 50

Ω to GND,

AC-Coupled, VID = 1 Vp-p,

DEM_x[1:0] = R, F(3)

0.8

1

1.2

Vp-p

Vtx-de-ratio_3.5

TX de-emphasis ratio

VOD = 1 Vp-p,

DEM_x[1:0] = R, F

–3.5

dB

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DS100MB203 Datasheet(PDF) 8 Page - Texas Instruments

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