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SN65DP141RLJT Datasheet(PDF) 11 Page - Texas Instruments |
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SN65DP141RLJT Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 32 page  48 k VCC IN ESD VCC 48 k ESD Gain Stage +EQ RBBDC VBB Self-Biasing Network Line End Termination VCC VCC ESD IN+ R = 50 T(SE) R = 50 T(SE) IN- PATTERN L= 2" OUT TEST CHANNEL CHARACTERIZATION BOARD SN65DP141 OSCILLOSCOPE GENERATOR L= 2" 11 SN65DP141 www.ti.com SLLSES6 – FEBRUARY 2016 Product Folder Links: SN65DP141 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Parameter Measurement Information (continued) Figure 11. Transmit Side Performance Test Circuit Figure 12. Equivalent Input Circuit SPACE Figure 13. 3-Level Input Biasing Network |
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