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SN65HVS885PWP Datasheet(PDF) 6 Page - Texas Instruments |
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SN65HVS885PWP Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 28 page  SN65HVS885 SLAS638A – JANUARY 2009 – REVISED OCTOBER 2015 www.ti.com Timing Requirements (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT tSU1 SIP to CLK setup time See Figure 7 4 ns tH1 SIP to CLK hold time See Figure 7 2 ns tSU2 Falling edge to rising edge (CE to CLK) setup time See Figure 8 4 ns tREC LD to CLK recovery time See Figure 5 2 ns fCLK Clock pulse frequency See Figure 6 DC 100 MHz 6.7 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH1, tPHL1 CLK to SOP CL = 15 pF, see Figure 6 10 ns tPLH2, tPHL2 LD to SOP CL = 15 pF, see Figure 4 14 ns tr, tf Rise and fall times CL = 15 pF, see Figure 6 6 ns 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: SN65HVS885 |
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