Host

Controller

TX Clock

SN65LVDS387 or 389

Target

Controller

Target

LVDS Receiver(s)

Indicates twisting of the

conductors.

T

T

T

T

T

Indicates the line termination

circuit.

Host

Balanced Interconnect

Power

Power

DB0

DB1

DB2

DBn–3

T

T

T

T

DBn–2

DBn–1

DBn

RX Clock

DB0

DB1

DB2

DBn–3

DBn–2

DBn–1

DBn

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

SN65LVDS387, SN75LVDS387, SN65LVDS389

SN75LVDS389, SN65LVDS391, SN75LVDS391

SLLS362G – SEPTEMBER 1999 – REVISED JANUARY 2016

SNx5LVDS3xx High-Speed Differential Line Drivers

1 Features

3 Description

This family of 4, 8, and 16 differential line drivers

1

•

Four ('391), Eight ('389), or Sixteen ('387) Line

implements the electrical characteristics of low-

Drivers Meet or Exceed the Requirements of ANSI

voltage differential signaling (LVDS). This signaling

EIA/TIA-644 Standard

technique lowers the output voltage levels of 5-V

•

Designed for Signaling Rates Up to 630 Mbps

differential standard levels (such as EIA/TIA-422B) to

With Very Low Radiation (EMI)

reduce the power, increase the switching speeds, and

allow operation with a 3.3-V supply rail. Any of the 16

•

Low-Voltage Differential Signaling With Typical

current-mode

drivers

will

deliver

a

minimum

Output Voltage of 350 mV and a 100-

Ω Load

differential output voltage magnitude of 247 mV into a

•

Propagation Delay Times Less Than 2.9 ns

100-

Ω load when enabled.

•

Output Skew Is Less Than 150 ps

Device Information(1)

•

Part-to-Part Skew Is Less Than 1.5 ns

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

35-mW Total Power Dissipation in Each Driver

SN65LVDS387

TSSOP (64)

17.00 mm × 6.10 mm

Operating at 200 MHz

SN75LVDS387

TSSOP (38)

9.70 mm × 4.40 mm

•

Driver Is High-Impedance When Disabled or With

SOIC (16)

9.90 mm × 3.91 mm

SN65LVDS389

TSSOP (16)

5.00 mm × 4.40 mm

•

SN65' Version Bus-Pin ESD Protection Exceeds

SN75LVDS389

TSSOP (64)

17.00 mm × 6.10 mm

15 kV

SN65LVDS391

TSSOP (38)

9.70 mm × 4.40 mm

•

Packaged in Thin Shrink Small-Outline Package

SOIC (16)

9.90 mm × 3.91 mm

With 20-mil Pin Pitch

SN75LVDS391

TSSOP (16)

5.00 mm × 4.40 mm

•

Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V

Tolerant

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

2 Applications

•

Wireless Infrastructure

•

Telecom Infrastructure

•

Printer

Typical Application Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.