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M95040-DWMN3TG Datasheet(PDF) 8 Page - STMicroelectronics |
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M95040-DWMN3TG Datasheet(HTML) 8 Page - STMicroelectronics |
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8 / 41 page  Signal description M95040-A125 M95040-A145 8/41 DocID024225 Rev 6 2 Signal description All input signals must be held high or low (according to voltages of VIH or VIL, as specified in Table 12 and Table 13). These signals are described below. 2.1 Serial Data output (Q) This output signal is used to transfer data serially out of the device during a Read operation. Data is shifted out on the falling edge of Serial Clock (C), most significant bit (MSB) first. In all other cases, the Serial Data output is in high impedance. 2.2 Serial Data input (D) This input signal is used to transfer data serially into the device. D input receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C), most significant bit (MSB) first. 2.3 Serial Clock (C) This input signal allows to synchronize the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). 2.4 Chip Select (S) Driving Chip Select (S) low selects the device in order to start communication. Driving Chip Select (S) high deselects the device and Serial Data output (Q) enters the high impedance state. 2.5 Hold (HOLD) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 2.6 Write Protect (W) This pin is used to write-protect the Status Register. 2.7 VSS ground VSS is the reference for all signals, including the VCC supply voltage. |
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