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SR1-UARU Datasheet(PDF) 6 Page - STMicroelectronics |
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SR1-UARU Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 21 page Pin descriptions SR1 6/21 DocID026048 Rev 2 3 Pin descriptions 3.1 Power supply (VCC) This pin is used to provide power to the Smart Reset device. A 0.1 µF ceramic decoupling capacitor is recommended to be connected between the VCC and VSS pins, as close to the SR1 device as possible. 3.2 Power-up sequence In normal mode, if different input side (SR) and VCC voltage domains are used, power-on sequence must avoid meeting the test mode entry condition to avoid inadvertent test mode entry: there should not be logic high present on the SR input before the VCC power-up. However VCC and V(SR) rising at the same time is OK (e.g. if both are in the same voltage domain), the device will then safely start into normal operating mode, with RST output inactive (in High-Z mode for open-drain option). 3.3 Ground (VSS) This is the ground pin for the device. 3.4 Smart Reset input (SR) Push-button Smart Reset input, active low with optional pull-up resistor. SR input needs to be asserted for at least tSRC to assert the reset output (RST). By connecting a voltage higher than VCC + 1.4 V to the SR input the device enters test mode (see Section 1: Description on page 3 for more information). 3.5 Reset output (RST) RST is active low or active high, open drain or push-pull reset output with optional internal pull-up resistor. Output reset pulse width is optional as follows: Neither fixed nor minimum output reset pulse duration (releasing the push-button while reset output is active, causes the output to de-assert) Fixed, factory-programmed output reset pulse duration for tREC independent on Smart Reset input state. 3.6 RST output undervoltage behavior (for open-drain option) High-Z on RST output below the specified operating voltage range is guaranteed at VCC power-on or in case that valid VCC dropped while the device was idle, i.e. while both output and input were inactive. |
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