C165H datasheet(5/499 Pages) INFINEON

Part #	C165H

Description	EMBEDDED C166 WITH USART IOM-2 AND HDLC SUPPORT

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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5 / 499 page

C165H

Page

Data Sheet

2001-04-19

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.2

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.3

Pinning Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.4

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.4.1

ISDN NT and PBX Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1

C165H Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2

C165H Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1

Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2

On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3

Clock Generation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.4

On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.5

Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1

Internal RAM and SFR Area

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.2

External Memory Space

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.3

Crossing Memory Boundaries

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

5

Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.1

Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.2

Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5.3

Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4

CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.5

PEC - Extension of Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6

Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.1

Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.2

Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3

Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

6.4

Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . . 105

6.5

Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . 108

6.6

Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.7

PEC Response Times

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

6.8

External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

6.8.1

Fast External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.8.2

External Interrupt Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

6.8.3

Interrupt Subnode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

6.8.4

The Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

6.9

Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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