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STM32F745VG Datasheet(PDF) 6 Page - STMicroelectronics

Part # STM32F745VG
Description  Up to 168 I/O ports with interrupt capability
Download  227 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F745VG Datasheet(HTML) 6 Page - STMicroelectronics

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List of tables
STM32F745xx STM32F746xx
6/227
DocID027590 Rev 4
List of tables
Table 1.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2.
STM32F745xx and STM32F746xx features and peripheral counts . . . . . . . . . . . . . . . . . . 13
Table 3.
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 27
Table 4.
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5.
Voltage regulator modes in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6.
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7.
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 8.
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9.
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 10.
STM32F745xx and STM32F746xx pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11.
FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 12.
STM32F745xx and STM32F746xx alternate function mapping . . . . . . . . . . . . . . . . . . . . . 76
Table 13.
STM32F745xx and STM32F746xx register boundary addresses. . . . . . . . . . . . . . . . . . . . 90
Table 14.
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 15.
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 16.
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 17.
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 18.
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 100
Table 19.
VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 20.
Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . 101
Table 21.
Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . 101
Table 22.
reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 23.
Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 24.
Typical and maximum current consumption in Run mode, code with data processing
running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 25.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 26.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . 106
Table 27.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . 107
Table 28.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART ON except prefetch / L1-cache ON)
or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 29.
Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 109
Table 30.
Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 109
Table 31.
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 110
Table 32.
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 111
Table 33.
Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 112
Table 34.
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 35.
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 36.
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 37.
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 38.
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 39.
HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 40.
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 41.
HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127


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