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HYB18L128160BF-75 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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HYB18L128160BF-75 Datasheet(HTML) 7 Page - Infineon Technologies AG |
7 / 53 page HY[B/E]18L128160B[C/F]-7.5 128-Mbit Mobile-RAM Overview Data Sheet 7 V1.4, 2004-04-30 1 Overview 1.1 Features • 4 banks × 2 Mbit × 16 organization • Fully synchronous to positive clock edge • Four internal banks for concurrent operation • Programmable CAS latency: 2, 3 • Programmable burst length: 1, 2, 4, 8 or full page • Programmable wrap sequence: sequential or interleaved • Programmable drive strength • Auto refresh and self refresh modes • 4096 refresh cycles / 64 ms • Auto precharge • Commerical (0°C to +70°C) and Extended (-25 oC to +85oC) operating temperature range • 54-ball P-VFBGA package (12.0 × 8.0 × 1.0 mm) Power Saving Features • Low supply voltages: V DD = 1.8 V ± 0.15 V, VDDQ = 1.8 V ± 0.15 V • Optimized self refresh ( I DD6) and standby currents (IDD2/IDD3) • Programmable Partial Array Self Refresh (PASR) • Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor • Power-Down and Deep Power Down modes Table 1 Performance Part Number Speed Code - 7.5 Unit Speed Grade 133 MHz Access Time ( t ACmax) CL = 3 5.4 ns CL = 2 6.0 ns Clock Cycle Time ( t CKmin) CL = 3 7.5 ns CL = 2 9.5 ns Table 2 Memory Addressing Scheme Item Addresses Banks BA0, BA1 Rows A0 - A11 Columns A0 - A8 |
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