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HYB18T1G160AF Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYB18T1G160AF Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 89 page Page 10 Rev. 1.02 May 2004 INFINEON Technologies HYB18T1G400/800/160AF 1Gb DDR2 SDRAM 1.6 Block Diagrams Block Diagram 64Mbit x 4 I/O x 4 Internal Memory Banks, (128 Mbit x 4 Organisation with 14 Row, 3 Bank and 12 Column External Addresses) 2 DQS CK, CK DLL RAS CAS CK CS WE CK Column-Address Counter/Latch Mode 11 A0-A13, BA0-BA2 CKE 17 17 I/O Gating DM Mask Logic Bank0 Memory Array (16384 x 512 x 16) Sense Amplifiers Bank0 Bank1 Bank7 17 9 2 2 2 4 4 4 Input Register 1 1 1 1 1 16 16 4 16 Data Mask Data CK, COL0,1 COL0,1 COL0,1 DQS Generator 1 1 4 16 DQ0-DQ3, DM DQS Write FIFO & Drivers Column Decoder 512 (x16) Registers 16384 CK 4 4 DQS DQS 1 1 4 4 4 4 4 4 4 4 AP 17 8 8 Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi- rectional DQ and DQS signals. |
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