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TPD3S714-Q1 Datasheet(PDF) 9 Page - Texas Instruments |
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TPD3S714-Q1 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 29 page 9 TPD3S714-Q1 www.ti.com SLVSCG4 – JANUARY 2016 Product Folder Links: TPD3S714-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 7.6 Timing Characteristics over operating free-air temperature range, EN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD-/D+/D-/VBUS_CON = float (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENABLE PIN tON Enable on time Time between enable device until FLT deasserts 13 ms OVER CURRENT PROTECTION tBLANK Overcurrent blanking time Time from overcurrent condition until FLT assertion and VBUS FET turn off 2 ms tRETRY Overcurrent retry time Time from overcurrent FET shut off until FET turns back on 100 ms tRECV Overcurrent recovery time Time from end of tRETRY until FLT deassertion if overcurrent condition is removed 8 ms OVER VOLTAGE PROTECTION tOVP_response OVP Response time - VBUS Measured from OVP Condition to FET turn off 2 4 µs tOVP_response OVP Response time - data switches Measured from OVP Condition to FET turn off 200 ns SHORT TO GROUND PROTECTION tSHRT Short to ground response time CLOAD = 0 uF, Time from short condition until current falls below 120% of ISHRT 2 4 µs |
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