Electronic Components Datasheet Search |
|
HYB25D128800AT-8 Datasheet(PDF) 10 Page - Infineon Technologies AG |
|
HYB25D128800AT-8 Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 79 page HYB25D128[400/800/160]A-[6/7/8] 128Mbit Double Data Rate SDRAM Pin Configuration Data Sheet 10 Rev. 1.06, 2004-01 09192003-LFQ1-R60G Figure 2 Block Diagram (32Mb × 4) 1 DQS CK, CK DLL RAS CAS CK CS WE CK Column-Address Counter/Latch Mode 11 A0-A11, BA0, BA1 CKE 12 14 I/O Gating DM Mask Logic Bank0 Memory Array (4096 x 1024 x 8) Sense Amplifiers Bank1 Bank2 Bank3 12 10 1 2 2 4 4 4 Input Register 1 1 1 1 1 8 8 2 8 clk out Data Mask Data CK, COL0 COL0 COL0 clk in DQS Generator 4 4 4 4 4 8 DQ0-DQ3, DM DQS 1 Write FIFO & Drivers Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does not represent an actual circuit implementation. Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals. Column Decoder 1024 (x8) Registers 4096 14 CK |
Similar Part No. - HYB25D128800AT-8 |
|
Similar Description - HYB25D128800AT-8 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |