HYB25D128800AT-8 datasheet(10/79 Pages) INFINEON

Part #	HYB25D128800AT-8

Description	128 Mbit Double Data Rate SDRAM

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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HYB25D128[400/800/160]A-[6/7/8]

128Mbit Double Data Rate SDRAM

Pin Configuration

Data Sheet

10

Rev. 1.06, 2004-01

09192003-LFQ1-R60G

Figure 2

Block Diagram (32Mb

× 4)

1

DQS

CK, CK

DLL

RAS

CAS

CK

CS

WE

CK

Column-Address

Counter/Latch

Mode

11

A0-A11,

BA0, BA1

CKE

12

14

I/O Gating

DM Mask Logic

Bank0

Memory

Array

(4096 x 1024 x 8)

Sense Amplifiers

Bank1

Bank2

Bank3

12

10

1

2

4

Input

Register

1

8

2

8

clk

out

Data

Mask

Data

CK,

COL0

clk

in

DQS

Generator

4

8

DQ0-DQ3,

DM

DQS

1

Write

FIFO

&

Drivers

Note: This Functional Block Diagram is intended to facilitate user understanding of the

operation of the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load

of the bidirectional DQ and DQS signals.

Column

Decoder

1024

(x8)

Registers

4096

14

CK

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