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HYB18T512400AF-5 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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HYB18T512400AF-5 Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 96 page  HYB18T512[400/800/160]A[C/F]–[3.7/5] 512-Mbit Double-Data-Rate-Two SDRAM Overview Data Sheet 7 Rev. 1.13, 2004-05 09112003-SDM9-IQ3P 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O • DRAM organisations with 4, 8 and 16 data in/outputs • Double Data Rate architecture: two data transfers per clock cycle, four internal banks for concurrent operation • CAS Latency: 3, 4 and 5 • Burst Length: 4 and 8 • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data. • DLL aligns DQ and DQS transitions with clock •DQS can be disabled for single-ended data strobe operation • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • Data masks (DM) for write data • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality. • Auto-Precharge operation for read and write bursts • Auto-Refresh, Self-Refresh and power saving Power-Down modes • Average Refresh Period 7.8 µs at a T CASE lower than 85 °C, 3.9 µs between 85 °C and 95 °C • Normal and Weak Strength Data-Output Drivers • 1K page size for ×4 & ×8, 2K page size for ×16 • Packages: P-TFBGA-60-6 for ×4 & ×8 components P-TFBGA-84-1 for ×16 components 1.2 Description The 512-Mb DDR2 DRAM is a high-speed Double- Data-Rate-2 CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O × 4 bank, 16 Mbit × 8I/O × 4bank or 8Mbit × 16 I/O × 4 bank chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures. The device is designed to comply with all DDR2 DRAM key features: 1. posted CAS with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. Off-Chip Driver (OCD) impedance adjustment and 5. an On-Die Termination (ODT) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. Table 1 High Performance Product Type Speed Code –3.7 –5 Units Speed Grade DDR2–533 4–4–4 DDR2–400 3–3–3 — max. Clock Frequency @CL5 f CK5 266 200 MHz @CL4 f CK4 266 200 MHz @CL3 f CK3 200 200 MHz min. RAS-CAS-Delay t RCD 15 15 ns min. Row Precharge Time t RP 15 15 ns min. Row Active Time t RAS 45 40 ns min. Row Cycle Time t RC 60 55 ns |
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