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HYB18T256400AF-3 Datasheet(PDF) 6 Page - Infineon Technologies AG |
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HYB18T256400AF-3 Datasheet(HTML) 6 Page - Infineon Technologies AG |
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6 / 90 page  Page 6 Rev. 1.02 May 2004 INFINEON Technologies HYB18T256400/800/160AF 256Mb DDR2 SDRAM 1.3 256Mbit DDR2 Addressing 1.4 Package Pinout & Addressing 1.4.1 Package Pinout for x4 components, 60 pins, FBGA Package (top view) Configuration 64Mb x 4 32Mb x 8 16Mb x 16 # of Banks 4 44 Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Auto-Precharge A10 / AP A10 / AP A10 / AP Row Address A0 ~ A12 A0 ~ A12 A0 ~ A12 Column Address A0 ~ A9, A11 A0 ~ A9 A0 ~ A8 Page Length 2048 bits 1024 bits 512 bits Page Size 1024 (1kB) 1024 (1kB) 1024 (1kB) page length = 2 colbit,, page size in bytes = 2 colbits x ORG / 8 where colbits is the number of column address bits and ORG the number of I/O (DQ) bits. 1 2 3 7 8 9 VDD NC VSS A VSSQ DQS VDDQ NC VSSQ DM B DQS VSSQ NC VDDQ DQ1 VDDQ C VDDQ DQ0 VDDQ NC VSSQ DQ3 D DQ2 VSSQ NC VDDL VREF VSS E VSSDL CK VDD CKE WE F RAS CK ODT RFU BA0 BA1 G CAS CS A10 A1 H A2 A0 VDD VSS A3 A5 J A6 A4 A7 A9 K A11 A8 VSS VDD A12 NC,(A14) L NC,(A15) NC,(A13) Notes: 1) VDDL and VSSDL are power and ground for the DLL.They are isolated on the device from VDD, VDDQ, VSS and VSSQ. 2) NC, (A13), NC,(A14) and NC,(A15) are additional address pins for future genera- tion DRAMs and are not connected on this component 3) Ball position G1 “RFU” will be used for BA2 on 1Gbit memory densities and higher |
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