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HYB25D128160AT-6 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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HYB25D128160AT-6 Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 79 page  HYB25D128[400/800/160]A-[6/7/8] 128Mbit Double Data Rate SDRAM Overview Data Sheet 7 Rev. 1.06, 2004-01 09192003-LFQ1-R60G coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Table 2 Ordering Information 1) 1) Low Power Versions have a “L” in the partnumber, for example HYB25D128400ATL-8. These components are specifically selected for low IDD6 Self Refresh currents. Type CAS Latency Clock (MHz) CAS Latency Clock (MHz) Speed Org. Package HYB25D128400AT(L)-8 2.5 125 2 100 DDR200 ×4 66 pin TSOP-II HYB25D128800AT(L)-8 ×8 HYB25D128160AT(L)-8 ×16 HYB25D128400AT(L)-7 143 133 DDR266A ×4 HYB25D128800AT(L)-7 ×8 HYB25D128160AT(L)-7 ×16 HYB25D128400AT(L)-6 166 133 DDR333 ×4 HYB25D128800AT(L)-6 ×8 HYB25D128160AT(L)-6 ×16 |
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