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STAP08DP5XTTR Datasheet(PDF) 7 Page - STMicroelectronics |
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STAP08DP5XTTR Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 28 page DocID024305 Rev 6 7/28 STAP08DP05 Maximum rating 28 3.3 Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Test conditions Min Typ Max Unit VDD Supply voltage 3.0 - 5.5 V VO Output voltage - 20 V IO Output current OUTn 5 - 100 mA IOH Output current SERIAL-OUT - +1 mA IOL Output current SERIAL-OUT - -1 mA VIH Input voltage 0.7 VDD -VDD+0.3 V VIL Input voltage -0.3 - 0.3VDD V twLAT LE/DM1 pulse width VDD = 3.0 to 5.0 V 20 - ns twCLK CLK pulse width 20 - ns twEN OE/DM2 pulse width 200 - ns tSETUP(D) Setup time for DATA 7 - ns tHOLD(D) Hold time for DATA 4 - ns tSETUP(L) Setup time for LATCH 15 - ns fCLK Clock frequency Cascade operation (1) 1. If the device is connected in cascade, it may not be possible to achieve the maximum data transfer. Please consider the timings carefully. -30 MHz |
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