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HYB39S128800CT-7.5 Datasheet(PDF) 7 Page - Infineon Technologies AG |
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HYB39S128800CT-7.5 Datasheet(HTML) 7 Page - Infineon Technologies AG |
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7 / 51 page  HYB 39S128400/800/160CT(L) 128-MBit Synchronous DRAM INFINEON Technologies 7 9.01 Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A11 Input Level – During a Bank Activate command cycle, A0 - A11 define the row address (RA0 - RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0 - CAn) when sampled at the rising clock edge.CAn depends upon the SDRAM organization: 32M x4 SDRAM CA0 - CA9, CA11 (Page Length = 2048 bits) 16M x8 SDRAM CA0 - CA9 (Page Length = 1024 bits) 8M x16 SDRAM CA0 = CA8 (Page Length = 512 bits) In addition to the column address, A10(= AP) is used to invoke the autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input Level – Bank Select Inputs. Selects which bank is to be active. DQx Input Output Level – Data Input/Output pins operate in the same manner as on conventional DRAMs. |
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