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HYB39S256160DTL-75 Datasheet(PDF) 6 Page - Infineon Technologies AG |
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HYB39S256160DTL-75 Datasheet(HTML) 6 Page - Infineon Technologies AG |
6 / 22 page INFINEON Technologies 6 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing) Memory Array Bank 1 8192 x 1024 x 8 Bit Memory Array Bank 2 8192 x 1024 x 8 Bit Memory Array Bank 3 8192 x 1024 x 8 Bit SPB04128 Column Address Counter Row Decoder Memory Array Bank 0 8192 x 1024 x 8 Bit Row Decoder Row Decoder Row Decoder Row Address Buffer Column Address Buffer Refresh Counter A0 - A12, BA0, BA1 A0 - A9, AP, BA0, BA1 Column Addresses Row Addresses Input Buffer Output Buffer DQ0 - DQ7 Control Logic & Timing Generator |
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