HYB39S256160DC-75 datasheet(9/22 Pages) INFINEON

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HYB39S256160DC-75 Datasheet(PDF) 9 Page - Infineon Technologies AG

Part #	HYB39S256160DC-75

Description	256 MBit Synchronous DRAM

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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INFINEON Technologies

2002-04-23

HYB39S256400/800/160DT(L)/DC(L)

256MBit Synchronous DRAM

DQM

LDQM

UDQM

Input

Pulse

Active

High

The Data Input/Output mask places the DQ buffers in a

high impedance state when sampled high. In Read mode,

DQM has a latency of two clock cycles and controls the

output buffers like an output enable. In Write mode, DQM

has a latency of zero and operates as a word mask by

allowing input data to be written if it is low but blocks the

write operation if DQM is high.

One DQM input is present in x4 and x8 SDRAMs, LDQM

and UDQM controls the lower and upper bytes in x16

SDRAMs.

VDD

VSS

Supply –

–

Power and ground for the input buffers and the core logic.

VDDQ

VSSQ

Supply –

–

Isolated power supply and ground for the output buffers to

provide improved noise immunity.

Type

Signal Polarity Function

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Infineon Technologies A...	HYB39S256160DC-75	630Kb / 28P	256-MBit Synchronous DRAM Rev. 1.02, Feb. 2004

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