Preliminary

Double-Data-Rate-Two SDRAM Micro-DIMM

DDR2 MDIMM

HYS64T32000[H/K/L]M–[3.7/5]–A

HYS64T64020[H/K/L]M–[3.7/5]–A

Data Sheet

6

Rev. 0.6, 2004-06

03242004-2CBE-IJ2X

1

Overview

This chapter gives an overview of the Double-Data-Rate-Two SDRAM Micro-DIMM product family and describes

its main characteristics.

1.1

Features

•

214-pin PC2-4200 and PC2-3200 DDR2 SDRAM

memory modules for use as main memory when

installed in systems such as mobile personal

computers.

•32M

× 64 and 64M × 64 module organisation and

32M

× 16 chip organisation

•

JEDEC standard Double-Data-Rate-Two

Synchronous DRAMs (DDR2 SDRAM) with a single

+ 1.8 V (± 0.1 V) power supply

•

Built with 512Mb DDR2 SDRAMs in P-TFBGA-84-2

chipsize packages

•

Programmable CAS Latencies (3, 4 and 5), Burst

Length (8 & 4) and Burst Type

•

Burst Refresh, Distributed Refresh and Self Refresh

•

All inputs and outputs SSTL_1.8 compatible

•

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

•

Serial Presence Detect with E

•

Micro-DIMM Dimensions (nominal) : 30 mm high,

54.0 mm wide

•

Based on JEDEC standard reference layouts Raw

Card “A” & “B”

•

2-piece type Mezzanine Socket with 0,4 mm

contact centers

1.2

Description

The

INFINEON

HYS64T[3200/6402]0[H/K/L]M–

[3.7/5]–A module family are low profile Unbuffered

Micro-DIMM modules “MDIMMs” with 30,0 mm height

based on DDR2 technology. DIMMs are available as

32M

× 64 and 64M × 64 organisation and density,

intended

for

mounting

into

214-pin

mezzanine

connector sockets.

The memory array is designed with 512Mb Double-

Data-Rate-Two

(DDR2)

Synchronous

DRAMs.

Decoupling capacitors are mounted on the PCB board.

The DIMMs feature serial presence detect based on a

serial E

first 128 bytes are programmed with configuration data

and are write protected; the

second 128 bytes are

available to the customer.

Table 1

Performance

Product Type Speed Code

–3.7

–5

Units

Speed Grade

PC2–4200 4–4–4

PC2–3200 3–3–3

—

max. Clock Frequency

@CL5

f

CK5

266

200

MHz

@CL4

f

CK4

266

200

MHz

@CL3

f

CK3

200

200

MHz

min. RAS-CAS-Delay

t

RCD

15

15

ns

min. Row Precharge Time

t

RP

15

15

ns

min. Row Active Time

t

RAS

45

45

ns

min. Row Cycle Time

t

RC

60

60

ns