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HYS64T32000LM-37-A Datasheet(PDF) 8 Page - Infineon Technologies AG |
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HYS64T32000LM-37-A Datasheet(HTML) 8 Page - Infineon Technologies AG |
8 / 31 page Preliminary HYS64T[3200/6402]0[H/K/L]M–[3.7/5]–A Double-Data-Rate-Two SDRAM Micro-DIMM Overview Data Sheet 8 Rev. 0.6, 2004-06 03242004-2CBE-IJ2X 1.3 Pin Configuration The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. Table 5 Pin Configuration of MDIMM Pin# Name Pin Type Buffer Type Function Clock Signals 122 CK0 I SSTL Clock Signals 1:0 194 CK1 I SSTL 123 CK0 ISSTL Complement Clock Signals 1:0 195 CK1 ISSTL 43 CKE0 I SSTL Clock Enables Note: 2-rank module 147 CKE1 I SSTL NC NC Note: 1-rank module Control Signals 165 S0 ISSTL Chip Select Rank 0 62 S1 ISSTL Chip Select Rank 1 Note: 2-rank module NC NC Note: 1-rank module 163 RAS ISSTL Row Address Strobe 60 CAS ISSTL Column Address Strobe 56 WE ISSTL Write Enable Address Signals 55 BA0 I SSTL Bank Address 1:0 162 BA1 I SSTL 161 A0 I SSTL Address Inputs 9:0 159 A1 I SSTL 52 A2 I SSTL 158 A3 I SSTL 51 A4 I SSTL 50 A5 I SSTL 157 A6 I SSTL 48 A7 I SSTL 155 A8 I SSTL 154 A9 I SSTL 54 A10 I SSTL Address Input 10/Autoprecharge AP I SSTL 47 A11 I SSTL Address Input 11 153 A12 I SSTL Address Input 12 |
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