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HYS72V64220GU-7-D Datasheet(PDF) 6 Page - Infineon Technologies AG |
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HYS72V64220GU-7-D Datasheet(HTML) 6 Page - Infineon Technologies AG |
6 / 15 page HYS 64/72V64220GU SDRAM-Modules INFINEON Technologies 6 9.01 Operating Currents per SDRAM Component T A = 0 to 70 oC, V DD = 3.3 V ± 0.3 V Parameter Test Condition Symbol -7/ -7.5 -8 Unit Note max. Operating current t RC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access – I CC1 230 170 mA 1, 2 Precharge stand-by current in Power Down Mode CS = V IH(MIN.), CKE ≤ VIL(MAX.) t CK =min. I CC2P 22 mA 1, 2 Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.), CKE ≥ VIH(MIN.) t CK =min. I CC2N 40 30 mA 1, 2 No operating current t CK = min., CS = VIH(MIN.), active state (max. 4 banks) CKE ≥ V IH(MIN.) I CC3N 50 45 mA 1, 2 CKE ≤ V IL(MAX.) I CC3P 10 10 mA 1, 2 Burst operating current t CK =min., Read command cycling – I CC4 150 100 mA 1,2,3 Auto refresh current t CK =min., Auto Refresh command cycling – I CC5 240 220 mA 1, 2 Self refresh current Self Refresh Mode, CKE = 0.2 V I CC6 33 mA 1 Notes 1. All values are shown per one SDRAM component. 2. These parameters depend on the cycle rate. These values are measured at 133 MHz operation frequency for -7 & -7.5 and at 100 MHz for -8 modules. Input signals are changed once during t CK, excepts for ICC6 and for stand-by currents when t CK = infinity. 3. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 are assumed and the data out current is excluded. |
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