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HYS72V16300GU-75-C2 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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HYS72V16300GU-75-C2 Datasheet(HTML) 10 Page - Infineon Technologies AG |
10 / 20 page HYS 64/72V16300/32220GU SDRAM-Modules INFINEON Technologies 10 9.01 CAS to CAS Delay Time (same bank) t CCD 1 – 1 – 1 – CLK – Refresh Cycle Refresh Period (4096 cycles) t REF – 64 – 64 – 64 ms Self-Refresh Exit Time t SREX 1 – 1 – 1 – CLK 10) Read Cycle Data Out Hold Time t OH 3 – 3 – 3 – ns 4) Data Out to Low Impedance t LZ 0 – 0 – 0 – ns – Data Out to High Impedance t HZ 373 738ns 11 DQM Data Out Disable Latency t DQZ – 2 – 2 – 2CLK – Write Cycle Data Input to Precharge (write recovery) t WR 2 – 2 – 2 – CLK – DQM Write Mask Latency t DQW 0 – 0 – 0 – CLK – AC Characteristics (cont’d) 3), 4) T A = 0 to 70 °C; VSS =0V; VDD =3.3 V ±0.3 V, tT =1ns Parameter Symbol Limit Values Unit Note -7 PC133-222 -7.5 PC133-333 -8 PC100-222 min. max. min. max. min. max. |
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