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HYS72V1283201GR-7-D Datasheet(PDF) 9 Page - Infineon Technologies AG |
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HYS72V1283201GR-7-D Datasheet(HTML) 9 Page - Infineon Technologies AG |
9 / 22 page HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules INFINEON Technologies 9 2002-07-18 Operating Currents per SDRAM Component T A =0 to 70 °C 1), V DD =3.3 V ± 0.3 V Parameter Test Condition Symbol 64 Mb 128 Mb 256 Mb 512 Mb Unit Note max. Operating current t RC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3. All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access – I CC1 110 160 270 tbd. mA 2) Precharge stand-by current in Power Down Mode CS = V IH(MIN.),CKE ≤ VIL(MAX.) t CK =min. I CC2P 21.5 2tbd. mA 2) Precharge Stand-by Current in Non-Power Down Mode CS = V IH (MIN.),CKE ≥ VIH(MIN.) t CK =min. I CC2N 40 40 25 tbd. mA 2) No operating current t CK =min., CS = VIH(MIN.), active state (max. 4 banks) CKE ≥ V IH(MIN.) I CC3N 50 50 50 tbd. mA 2) CKE ≤ V IL(MAX.) I CC3P 8 1010tbd. mA 2) Burst operating current t CK =min., Read command cycling – I CC4 70 100 170 tbd. mA 2), 3) Auto refresh current t CK =min., Auto Refresh command cycling – I CC5 140 230 240 tbd. mA 2) Self refresh current Self Refresh Mode,CKE = 0.2 V – I CC6 1 1.5 2.5 tbd. mA 2) |
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