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PEB20532 Datasheet(PDF) 9 Page - Infineon Technologies AG |
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PEB20532 Datasheet(HTML) 9 Page - Infineon Technologies AG |
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9 / 282 page  PEB 20532 PEF 20532 List of Figures Page Data Sheet 9 2000-09-14 Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 3 System Integration With External DMA Controller . . . . . . . . . . . . . . . . 23 Figure 4 Point-to-Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 5 Point-to-Multipoint Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 6 Multimaster Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7 Pin Configuration P-TQFP-100-3 Package . . . . . . . . . . . . . . . . . . . . . 27 Figure 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 9 SCC Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 10 SCC Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 11 XFIFO/RFIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . 45 Figure 12 XFIFO/RFIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . 45 Figure 13 Clock Supply Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 14 Clock Mode 0a/0b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 15 Clock Mode 1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 16 Clock Mode 2a/2b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 17 Clock Mode 3a/3b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 18 Clock Mode 4 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 19 Selecting one time-slot of programmable delay and width . . . . . . . . . 56 Figure 20 Selecting one or more time-slots of 8-bit width . . . . . . . . . . . . . . . . . . 58 Figure 21 Clock Mode 5a Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 22 Clock Mode 5a "Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 23 Clock Mode 5a "Non Continuous Mode" . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 24 Selecting one or more octet wide time-slots . . . . . . . . . . . . . . . . . . . . 63 Figure 25 Clock Mode 5b Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 26 Clock Mode 6a/6b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 27 Clock Mode 7a/7b Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 28 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) . . . 69 Figure 29 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Disabled) . . . 69 Figure 30 DPLL Algorithm for FM0, FM1 and Manchester Encoding . . . . . . . . . 70 Figure 31 Request-to-Send in Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 32 NRZ and NRZI Data Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 33 FM0 and FM1 Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 34 Manchester Data Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 35 RTS/CTS Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 36 SCC Test Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 37 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 38 HDLC Receive Data Processing in 16 bit Automode . . . . . . . . . . . . . . 85 Figure 39 HDLC Receive Data Processing in 8 bit Automode . . . . . . . . . . . . . . . 85 Figure 40 HDLC Receive Data Processing in Address Mode 2 (16 bit). . . . . . . . 86 Figure 41 HDLC Receive Data Processing in Address Mode 2 (8 bit). . . . . . . . . 86 Figure 42 HDLC Receive Data Processing in Address Mode 1 . . . . . . . . . . . . . . 86 |
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Similar Description - PEB20532 |
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