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SN74HC74 Datasheet(PDF) 11 Page - Texas Instruments

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Part # SN74HC74
Description  Dual D-Type Positive-Edge-Triggered Flip-Flops
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74HC74 Datasheet(HTML) 11 Page - Texas Instruments

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5 V
5 V
5 V
SN74HC74
SN74LVC1G17
SN54HC74, SN74HC74
www.ti.com
SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
The resistor and capacitor at the CLR pin are optional. If they are not used, the CLR pin should be connected
directly to VCC to be inactive.
9.2 Typical Application
Figure 4. Device Power Button Circuit
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. Outputs may be combined to produce higher drive, but the
high drive will also create faster edges into light loads. Because of this, routing and load conditions should be
considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
For rise time and fall time specifications, see (
Δt/ΔV) in Recommended Operating Conditions table.
For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions:
Load currents should not exceed 25 mA per output and 50 mA total for the part.
Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
Copyright © 1982–2015, Texas Instruments Incorporated
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