SN54LV240A, SN74LV240A

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SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015

7.3 Recommended Operating Conditions

see

(1)

MIN

MAX

UNIT

Supply voltage

2

5.5

V

1.5

High-level input voltage

V

0.5

Low-level input voltage

V

Input voltage

0

5.5

V

High or low state

0

Output voltage

V

3-state

0

5.5

–50

µA

–2

High-level output current

–8

mA

–16

50

µA

2

Low-level output current

8

mA

16

200

Δt/Δv

Input transition rise or fall rate

100

ns/V

20

SN54LV240A

–55

125

Operating free-air temperature

°C

SN74LV240A

–40

125

(1)

Implications of Slow or Floating CMOS Inputs, SCBA004.

7.4 Thermal Information

DW

DB

DGV

NS

PW

UNIT

20 PINS

79.2

94.5

116.2

76.7

102.4

Junction-to-case (top) thermal resistance

43.7

56.4

31.2

43.2

36.5

Junction-to-board thermal resistance

47.0

49.7

57.7

44.2

53.6

°C/W

Junction-to-top characterization parameter

18.6

18.5

0.9

16.8

2.4

Junction-to-board characterization parameter

46.5

49.3

57.0

43.8

52.9

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The package thermal impedance is calculated in accordance with JESD 51-7.

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