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SN74LV74ARGYR Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LV74ARGYR Datasheet(HTML) 1 Page - Texas Instruments |
1 / 31 page TG C C TG C TG C C C C TG C C PRE CLK D CLR Q Q C Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54LV74A, SN74LV74A SCLS381M – AUGUST 1997 – REVISED MARCH 2015 SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops 1 Features 3 Description These dual positive-edge-triggered D-type flip-flops 1 • 2-V to 5.5-V VCC Operation are designed for 2-V to 5.5-V VCC operation. • Maximum tpd of 8.5 ns at 5 V • Typical VOLP (Output Ground Bounce) Device Information(1) < 0.8 V at VCC = 3.3 V, TA = 25°C PART NUMBER PACKAGE BODY SIZE (NOM) • Typical VOHV (Output VOH Undershoot) VQFN (14) 3.50 mm × 3.50 mm > 2.3 V at VCC = 3.3 V, TA = 25°C SOIC (14) 8.65 mm × 3.91 mm • Support Mixed-Mode Voltage Operation on SN74LV74A SOP (14) 10.30 mm × 5.30 mm All Ports SSOP (14) 6.20 mm × 5.30 mm • Ioff Supports Partial-Power-Down TSSOP (14) 5.00 mm × 4.40 mm Mode Operation (1) For all available packages, see the orderable addendum at • Latch-up Performance Exceeds 250 mA the end of the data sheet. Per JESD 17 Logic Diagram, Each Flip-Flop • ESD Protection Exceeds JESD 22 (Positive Logic) – 2000-V Human-Body Model (A114-A) – 500-V Charged-Device Model (C101) 2 Applications • Programmable Logic Controller (PLC) • DCS and PAC: Analog Input Module • AV Receiver • Server PSU • STB, DVR, and Streaming Media (Withdraw) • Server Motherboard 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. |
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