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SN54LV74A, SN74LV74A

SCLS381M – AUGUST 1997 – REVISED MARCH 2015

SNx4LV74A Dual Positive-Edge-Triggered D-Type Flip-Flops

1 Features

3 Description

These dual positive-edge-triggered D-type flip-flops

1

•

•

•

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

VQFN (14)

3.50 mm × 3.50 mm

SOIC (14)

8.65 mm × 3.91 mm

•

Support Mixed-Mode Voltage Operation on

SN74LV74A

SOP (14)

10.30 mm × 5.30 mm

All Ports

SSOP (14)

6.20 mm × 5.30 mm

•

TSSOP (14)

5.00 mm × 4.40 mm

Mode Operation

(1) For all available packages, see the orderable addendum at

•

Latch-up Performance Exceeds 250 mA

the end of the data sheet.

Per JESD 17

Logic Diagram, Each Flip-Flop

•

ESD Protection Exceeds JESD 22

(Positive Logic)

–

2000-V Human-Body Model (A114-A)

–

500-V Charged-Device Model (C101)

2 Applications

•

Programmable Logic Controller (PLC)

•

DCS and PAC: Analog Input Module

•

AV Receiver

•

Server PSU

•

STB, DVR, and Streaming Media (Withdraw)

•

Server Motherboard

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.