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SN74LV125APW Datasheet(PDF) 9 Page - Texas Instruments |
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SN74LV125APW Datasheet(HTML) 9 Page - Texas Instruments |
9 / 29 page 2A 2Y 2OE 1A 1Y 1OE 4A 4Y 4OE 3A 3Y 3OE 9 SN74LV125A www.ti.com SCES124N – DECEMBER 1997 – REVISED JANUARY 2016 Product Folder Links: SN74LV125A Submit Documentation Feedback Copyright © 1997–2016, Texas Instruments Incorporated 9 Detailed Description 9.1 Overview The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation. These devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 9.2 Functional Block Diagram Figure 4. Logic Diagram (Positive Logic) 9.3 Feature Description • Wide operating voltage range – Operates from 2 V to 5.5 V • Allows down-voltage translation – Inputs accept voltages to 5.5 V • Ioff Feature – Supports Live Insertion, Partial Power-Down Mode, and Back-Drive Protection 9.4 Device Functional Modes Table 1. Function Table (Each Buffer) INPUTS OUTPUT Y OE A L H H L L L H X Z |
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