PEF22554E datasheet(9/30 Pages) INFINEON

Part #	PEF22554E

Description	Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

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Manufacturer	INFINEON [Infineon Technologies AG]

Direct Link	http://www.infineon.com

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QuadFALC®

PEF 22554

Overview

Delta Sheet

9/30

2002-09-16

A6

138

RL1.2

I (analog)

Line Receiver 1, Channel 2

P6

43

RL1.3

I (analog)

Line Receiver 1, Channel 3

P9

66

RL1.4

I (analog)

Line Receiver 1, Channel 4

A8

116

RL2.1

I (analog)

Line Receiver 2, Channel 1

A7

137

RL2.2

I (analog)

Line Receiver 2, Channel 2

P7

44

RL2.3

I (analog)

Line Receiver 2, Channel 3

P8

65

RL2.4

I (analog)

Line Receiver 2, Channel 4

A13

109

XL1.1

O (analog) Transmit Line 1, Channel 1

A2

144

XL1.2

O (analog) Transmit Line 1, Channel 2

P2

37

XL1.3

O (analog) Transmit Line 1, Channel 3

P13

72

XL1.4

O (analog) Transmit Line 1, Channel 4

A12

111

XL2.1

O (analog) Transmit Line 2, Channel 1

A3

142

XL2.2

O (analog) Transmit Line 2, Channel 2

P3

39

XL2.3

O (analog) Transmit Line 2, Channel 3

P12

70

XL2.4

O (analog) Transmit Line 2, Channel 4

B4

133

MCLK

I

Master Clock

N6

48

SYNC

I + PU

Clock Synchronization of DCO-R

L10

69

SEC/FSC

I/O + PU

One-Second Timer Input

One-Second Timer Output

8 kHz Frame Synchronization Output

D10

119

RCLK1

O + PU

Receive Clock, Channel 1

D7

130

RCLK2

O + PU

Receive Clock, Channel 2

L5

47

RCLK3

O + PU

Receive Clock, Channel 3

N9

61

RCLK4

O + PU

Receive Clock, Channel 4

E1

9

RDO1

O

Receive Data Out, Channel 1

F1

12

RDO2

O

Receive Data Out, Channel 2

K1

27

RDO3

O

Receive Data Out, Channel 3

K4

30

RDO4

O

Receive Data Out, Channel 4

E2

8

SCLKR1

I/O + PU

System Clock Receive, Ch. 1

Table 2

BGA Pin Assignment (cont’d)

Ball No.

BGA

Pin No.

TQFP

Symbol

Input(I)

Output(O)

Supply(S)

Function

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