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IR38060MTRPBF Datasheet(PDF) 4 Page - Infineon Technologies AG |
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IR38060MTRPBF Datasheet(HTML) 4 Page - Infineon Technologies AG |
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4 / 66 page  IR38060 4 Rev 3.5 Feb 11, 2016 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 PVIN Input voltage for power stage. Bypass capacitors between PVin and PGND should be connected very close to this pin and PGND. 2 Boot Supply voltage for high side driver 3 Track_En ¯¯¯¯¯¯¯¯¯ Pull low to enable tracking function. Leave floating to disable tracking function. 4 Vp Used for sequencing and tracking applications. Leave open if not used. 5 Vsns Sense pin for OVP and PGood 6 FB Inverting input to the error amplifier. This pin is connected directly to the output of the regulator or to the output of the remote sense amplifier, via resistor divider to set the output voltage and provide feedback to the error amplifier. 7 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to FB to provide loop compensation. 8 RSo Remote Sense Amplifier Output 9 RS- Remote Sense Amplifier input. Connect to ground at the load. 10 RS+ Remote Sense Amplifier input. Connect to output at the load. 11 PGood Power Good status pin. Output is open drain. Connect a pull up resistor from this pin to VCC. 12,23, 25 PGND Power ground. This pin should be connected to the system’s power ground plane. Bypass capacitors between PVin and PGND should be connected very close to the PVIN pin (pin 1) and this pin. 13 LGND Signal ground for internal reference and control circuitry. 14 RT/Sync In analog mode, use an external resistor from this pin to GND to set the switching frequency. The resistor should be placed very close to the pin. This pin can also be used for external synchronization. No resistor is used in digital mode. 15 EN/FCCM Enable pin to turn on and off the IC. In analog mode, also serves as a mode pin, forcing the converter to operate in CCM when pulled to<3.1V. 16 ADDR Sets PMBus address for the device; should be floated if digital communication is not needed. 17 SALERT ¯¯¯¯¯¯¯ /TMON SMBus Alert ¯¯¯¯ line; pin provides a voltage proportional to the junction temperature if digital communication is not needed. 18 SDA/IMON SMBus data serial input/output line; pin provides a voltage proportional to the output current if digital communication is not needed. 19 SCL/OCSet SMBus clock line; used to set OC thresholds if digital communication is not needed. 20 P1V8 This is the supply for the digital circuits; bypass with a 2.2uF capacitor to LGnd 21 Vin Input Voltage for LDO. 22 VCC Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from this pin to PGnd. 24 SW Switch node. This pin is connected to the output inductor. 26 NC NC |
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