Unit LoadingFan Out

Pin

54F74F

Names

Description

UL

HIGHLOW

Mode Control Inputs

1010

Parallel Data Inputs

1010

Serial Data Input (Shift Right)

1010

Serial Data Input (Shift Left)

1010

CP

Clock Pulse Input (Active Rising Edge)

1010

MR

Asynchronous Master Reset Input (Active LOW)

1010

Parallel Outputs

50333

b

1 mA20 mA

Functional Description

The ’F194 contains four edge-triggered D flip-flops and the

necessary interstage logic to synchronously perform shift

right shift left parallel load and hold operations Signals

operation as shown in the Mode Select Table Signals on

inputs can change when the clock is in either state provid-

ed only that the recommended setup and hold times with

respect to the clock rising edge are observed A LOW sig-

nal on Master Reset (MR) overrides all other inputs and

forces the outputs LOW

Mode Select Table

Operating

Inputs

Outputs

Mode

MR

Reset

L

X

X

X

X

X

LLLL

Hold

H

l

l

X

X

X

Shift Left

H

h

l

X

l

X

L

Hh

l

X

h

X

H

Shift Right

H

l

h

l

X

X

L

Hl

h

h

X

X

H

Parallel Load

H

h

h

X

X

Logic Diagram

TLF9498 – 4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays

2