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PXB4360F Datasheet(PDF) 3 Page - Infineon Technologies AG |
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PXB4360F Datasheet(HTML) 3 Page - Infineon Technologies AG |
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3 / 66 page  3;%) 7DEOH RI &RQWHQWV 3DJH Data Sheet 0-3 07.2000 2YHUYLHZ 1.1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6\VWHP,QWHJUDWLRQ )XQFWLRQDO2YHUYLHZ 'DWD)ORZ DQG)XQFWLRQDO'HVFULSWLRQRI WKH &$0( 4.1 Programming of the Search and Search Result Pattern . . . . . . . . . . . . . . . . . . . . 20 4.2 Reading the Search Pattern for a Predefined LCI Value . . . . . . . . . . . . . . . . . . . 21 4.3 Configuration and Testing of the CAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Search Operation for Cell Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4.1 Data Structure of Request Commands for 16-Bit Mode . . . . . . . . . . . . . . . . . . . . 23 4.4.2 Data Structure of the Request Commands for 32-Bit Mode . . . . . . . . . . . . . . . . . 25 5HJLVWHUV 5.1 Write Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Search Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Address Register (DLCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.4 Search Result Data Register (SLCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 Read Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 Description of Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6.1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.7 Testmode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7.1 Data Field of Testmode Register (Selection is MODE) . . . . . . . . . . . . . . . . . . . . 39 5.7.2 Data Field of Testmode Register (Selection is TMODE) . . . . . . . . . . . . . . . . . . . 41 5.7.3 Data Field of Testmode Register (Selection is TMUX) . . . . . . . . . . . . . . . . . . . . . 42 5.7.4 Data Field of Testmode Register (Selection is VER0) . . . . . . . . . . . . . . . . . . . . . 42 5.7.5 Data Field of Testmode Register (Selection is VER1) . . . . . . . . . . . . . . . . . . . . . 43 5.7.6 Data Field of Testmode Register (Selection is VER2) . . . . . . . . . . . . . . . . . . . . . 43 5.7.7 Data Field of Testmode Register (Selection is VER3) . . . . . . . . . . . . . . . . . . . . . 44 ,QWHUIDFH 'HVFULSWLRQ 6.1 Data Bus and Address Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 Cascade Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.1 Cascade Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4 Boundary Scan Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.5 Microprocessor and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.6 Reference for Internal Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 |
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