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SAF82526N Datasheet(PDF) 3 Page - Infineon Technologies AG |
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SAF82526N Datasheet(HTML) 3 Page - Infineon Technologies AG |
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3 / 126 page  General Information Semiconductor Group 3 Table of Contents Page 1Features ..................................................................................................................... 6 1.1 Pin Definitions and Functions ................................................................................... 10 1.2 System Integration .................................................................................................... 17 1.3 Functional Description .............................................................................................. 22 2 Operating Modes ..................................................................................................... 24 2.1 Auto-Mode (MODE: MDS1, MDS0 = 00) .................................................................. 24 2.2 Non-Auto Mode (MODE: MDS1, MDS0 = 01) .......................................................... 24 2.3 Transparent Mode 1 (MODE: MDS1, MDS0, ADM = 101) ....................................... 25 2.4 Transparent Mode 0 (MODE: MDS1, MDS0, ADM = 100) ....................................... 25 2.5 Extended Transparent Modes 0; 1 (MODE: MDS1, MDS0 = 11) ............................. 25 2.6 Receive Data Flow (Summary) ................................................................................. 26 2.7 Transmit Data Flow ................................................................................................... 27 3 Procedural Support (Layer-2 Functions) .............................................................. 28 3.1 Full-Duplex LAPB/LAPD Operation .......................................................................... 28 3.2 Half-Duplex SDLC-NRM Operation .......................................................................... 34 3.3 Error Handling ........................................................................................................... 38 4 CPU Interface .......................................................................................................... 38 4.1 Register Set .............................................................................................................. 38 4.2 Data Transfer Modes ................................................................................................. 38 4.3 Interrupt Interface ...................................................................................................... 39 4.4 DMA Interface ........................................................................................................... 43 4.5 FIFO Structure .......................................................................................................... 47 5 Serial Interface (Layer-1 Functions) ...................................................................... 49 5.1 Clock Modes .............................................................................................................. 49 5.2 Clock Recovery (DPLL) ............................................................................................ 57 5.3 Bus Configuration ..................................................................................................... 60 5.4 Data Encoding .......................................................................................................... 63 5.5 Modem Control Functions (RTS/CTS, CD) ............................................................... 63 6 Special Functions ................................................................................................... 65 6.1 Fully Transparent Transmission and Reception ....................................................... 65 6.2 Cyclic Transmission (Fully Transparent) ................................................................... 65 6.3 Continuous Transmission (DMA Mode only) ............................................................ 66 6.4 Receive Length Check Feature ................................................................................ 66 6.5 One Bit Insertion ....................................................................................................... 67 6.6 Data Inversion........................................................................................................... 67 |
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