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SN74LVC1G32DCKRG4 Datasheet(PDF) 10 Page - Texas Instruments |
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SN74LVC1G32DCKRG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 39 page Y = A + B or Y = • A B SN74LVC1G32 SCES219V – APRIL 1999 – REVISED AUGUST 2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC1G32 device contains one 2-input positive OR gate device and performs the Boolean function . This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm. 8.2 Functional Block Diagram 8.3 Feature Description • Wide operating voltage range. – Operates from 1.65 V to 5.5 V. • Allows down voltage translation. • Inputs accept voltages to 5.5 V. • Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V. 8.4 Device Functional Modes Function Table INPUTS OUTPUT Y A B H X H X H H L L L 10 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G32 |
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