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F28M36P63C2ZWTT Datasheet(PDF) 6 Page - Texas Instruments

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Part # F28M36P63C2ZWTT
Description  Concerto Microcontrollers
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

F28M36P63C2ZWTT Datasheet(HTML) 6 Page - Texas Instruments

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F28M36P63C2, F28M36P53C2, F28M36H53C2, F28M36H53B2
F28M36H33C2, F28M36H33B2
SPRS825D – OCTOBER 2012 – REVISED OCTOBER 2015
www.ti.com
Section 5.9.4 (Flash Timing – Master Subsystem): Removed "Master Subsystem – Flash/OTP Endurance for T
Temperature Material" table (Table 6-16 in SPRS825C).
..................................................................... 58
Section 5.9.4: Removed "Master Subsystem – Flash/OTP Endurance for S Temperature Material" table (Table
6-17 in SPRS825C).
............................................................................................................... 58
Section 5.9.4: Removed "Master Subsystem – Flash Parameters at 125 MHz" table (Table 6-20 in SPRS825C).
.. 58
Table 5-16 (Master Subsystem – Flash/OTP Endurance): Changed title from "Master Subsystem – Flash/OTP
Endurance for Q Temperature Material" to "Master Subsystem – Flash/OTP Endurance".
.............................. 58
Table 5-16: Removed "ERASE/PROGRAM TEMPERATURE" column.
.................................................... 58
Table 5-16: Removed footnote.
................................................................................................... 58
Table 5-17 (Master Subsystem – Flash Parameters): Changed title from "Master Subsystem – Flash Parameters
at 75 MHz" to "Master Subsystem – Flash Parameters".
..................................................................... 58
Table 5-17: Updated table.
........................................................................................................ 58
Table 5-17: Updated "Program time includes overhead ..." footnote
......................................................... 58
Table 5-17: Added footnote about current and Flash API
..................................................................... 58
Section 5.9.5 (Flash Timing – Control Subsystem): Removed "Control Subsystem – Flash/OTP Endurance for T
Temperature Material" table (Table 6-24 in SPRS825C).
..................................................................... 60
Section 5.9.5: Removed "Control Subsystem – Flash/OTP Endurance for S Temperature Material" table (Table
6-25 in SPRS825C).
............................................................................................................... 60
Section 5.9.5: Removed "Control Subsystem – Flash Parameters at 150 MHz" table (Table 6-28 in SPRS825C).
.. 60
Table 5-21 (Control Subsystem – Flash/OTP Endurance): Changed title from "Control Subsystem – Flash/OTP
Endurance for Q Temperature Material" to "Control Subsystem – Flash/OTP Endurance".
............................. 60
Table 5-21: Removed "ERASE/PROGRAM TEMPERATURE" column.
.................................................... 60
Table 5-21: Removed footnote.
................................................................................................... 60
Table 5-22 (Control Subsystem – Flash Parameters): Changed title from "Control Subsystem – Flash
Parameters at 100 MHz" to "Control Subsystem – Flash Parameters".
.................................................... 60
Table 5-22: Updated table.
........................................................................................................ 60
Table 5-22: Updated "Program time includes overhead ..." footnote.
....................................................... 60
Table 5-22: Added footnote about current and Flash API,
.................................................................... 60
Section 5.11.4 (Cortex-M3 Controller Area Network): Added NOTE about CAN and D_CAN.
........................ 118
Section 5.12.7.1.2 (McBSP as SPI Master or Slave Timing): Replaced "For all SPI slave modes ..." paragraphs
with "For all SPI slave modes ..." table footnotes.
............................................................................ 158
Table 5-81 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Added "For all
SPI slave modes ..." footnote.
................................................................................................... 158
Table 5-83 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Added "For all
SPI slave modes ..." footnote.
................................................................................................... 159
Table 5-85 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Added "For all
SPI slave modes ..." footnote.
................................................................................................... 160
Table 5-87 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Added "For all
SPI slave modes ..." footnote.
................................................................................................... 161
Table 6-2 (Control Subsystem Peripheral Frame 0): Changed title from "Control Subsystem Peripheral Frame 0
(Includes Analog)" to "Control Subsystem Peripheral Frame 0".
........................................................... 163
Table 6-2: 0000 1780 – 0000 17FF: Changed register name from "C Hardware Logic BIST Registers" to
"Hardware BIST Registers".
...................................................................................................... 163
Table 6-10 (Master Subsystem Peripherals): 400F B000 – 400F B1FF: Changed "PBIST Control Registers" to
"Reserved".
........................................................................................................................ 171
Table 6-10: 400F BB00 – 400F BBFF: Changed "M HWBIST Registers" to "Reserved".
.............................. 171
Section 6.2 (Identification): Added section.
.................................................................................... 173
Table 6-14 (Interrupts from NVIC to Cortex-M3): Interrupt Number 91: Changed "PBIST Done" to "Reserved".
... 176
Section 6.4.2 (C28x Core Hardware Built-In Self-Test): Updated section.
................................................ 182
Section 6.9.3 (Analog and Digital Subsystems' Power-On-Reset Functionality): Added statement clarifying that
POR is always enabled.
.......................................................................................................... 197
Figure 6-7 (Connecting Input Clocks to a Concerto Device): Updated figure
............................................. 198
Section 6.10.3 (External Oscillators (Pins X1, VSSOSC, XCLKIN)): Updated section ...................................... 199
Section 6.10.4 (Main PLL): Changed the maximum Main PLL output clock from 550 MHz to 300 MHz.
............. 199
Figure 6-8 (Main PLL): Changed the maximum Main PLL output clock from 550 MHz to 300 MHz.
.................. 200
Section 6.12.3 (C28x STANDBY Mode): Changed MTOCIPCINT1 to MTOCIPCINT2
.................................. 215
Table 6-31 (AIO_MUX1 Pin Assignments (C28x AIO Modes)): Changed ADC2INB2 to ADC1INB2 in Device Pin
Name column and C28x AIO Mode 1 column
................................................................................. 236
Table 6-31: Changed ADC2INB6 to ADC1INB6 in Device Pin Name column and C28x AIO Mode 1 column
....... 236
Section 7 (Applications, Implementation, and Layout): Added section.
.................................................... 244
6
Revision History
Copyright © 2012–2015, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C2 F28M36P53C2 F28M36H53C2 F28M36H53B2 F28M36H33C2 F28M36H33B2


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