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RM44L920APGET Datasheet(PDF) 8 Page - Texas Instruments |
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RM44L920APGET Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 158 page  RM44L920, RM44L520 SPNS229B – OCTOBER 2014 – REVISED NOVEMBER 2015 www.ti.com • Table 6-25 (PBIST RAM Grouping): Added table notes identifying address ranges of ESRAM PBIST groups ........ 71 • Table 6-25: Added missing values for PBIST_ROM and STC_ROM ........................................................ 71 • Table 6-32 (Reset/Abort/Error Sources): Added POWER DOMAIN CONTROL rows .................................... 85 • Section 6.20.3 (JTAG Identification Code): Added Table 6-34, JTAG ID Code ............................................ 88 • Table 6-36 (JTAG Scan Interface Timing): Updated/Changed NO. 2, tsu(TDI/TMS - RTCKr) MIN from "21" to "26" ns ................................................................................................................................ 90 • Table 6-36: Updated/Changed NO. 5, td(TCKf -TDO) MAX from "10" to "12" ns .......................................... 90 • Table 7-2 (Switching Characteristics for Output Timings versus Load Capacitance (CL)): Corrected the rise/fall times of the 8/2 mA buffers in 8 mA mode ....................................................................................... 94 • Figure 7-3 (ePWMx Module Interconnections): Added footnote A, ePWMx Input Synchronziation Selection detail reference ............................................................................................................................. 96 • Figure 7-4 (ePWMx Input Synchronization Selection Detail): Added paragraph and new figure ......................... 96 • Table 7-6 (Connection to ePWMx Modules for Device-Level Trip Zone Inputs): Add "filter width is 6 VCLK4 cycles" footnote ...................................................................................................................... 99 • Table 7-8 (ePWMx Timing Requirements): Added "filter width is 6 VCLK4 cycles" footnote ............................ 101 • Table 7-10 (ePWMx Trip-Zone Timing Requirements): Updated/Change tw(TZ) Asynchronous MIN value ............ 101 • Table 7-10: Add "filter width is 6 VCLK4 cycles" footnote .................................................................... 101 • Figure 7-3 (eCAPx Module Interconnections): Added footnote A, eCAPx Input Synchronziation Selection detail reference ............................................................................................................................ 102 • Figure 7-7 (eCAPx Input Synchronization Selection Detail): Added paragraph and new figure ........................ 102 • Table 7-12 (Device-Level Input Connection to eCAPx Modules): Add "filter width is 6 VCLK4 cycles" footnote ..... 103 • Table 7-13 (eCAPx Timing Requirements): Add "filter width is 6 VCLK4 cycles" footnote .............................. 104 • Figure 7-8 (eQEP Module Interconnections): Added footnote A, eQEPx Input Synchronziation Selection detail ... 105 • Figure 7-9 (eQEPx Input Synchronization Selection Detail): Added paragraph and new figure ........................ 105 • Table 7-16 (Device-Level Input Connection to eQEPx Modules): Add "filter width is 6 VCLK4 cycles" footnote ..... 106 • Table 7-17 (eQEPx Timing Requirements): Added "filter width is 6 VCLK4 cycles" footnote .......................... 106 • Section 7.5.2.1 (MibADC1 Event Trigger Hookup): NOTE: Updated/Changed "ePWM_S2" to "ePWM_A2" ......... 109 • Table 7-21 (MibADC2 Event Trigger Hookup): Updated/Changed "AD1EVT" to "AD2EVT" for Option A and Option B of EVSRC 000 .......................................................................................................... 110 • Section 7.5.2.2 (MibADC2 Event Trigger Hookup): NOTE: Updated/Changed "ePWM_S2" to "ePWM_A2" ......... 110 • Table 7-23 (MibADC Recommended Operating Conditions): Added associated footnotes to VCCAD MAX, VSSAD MIN, and IAIC........................................................................................................................ 113 • Table 7-24 (MibADC Electrical Characteristics): Updated/Changed the VCCAD = 5.5 V maximum test condition..... 113 • Table 7-26 (MibADC Operating Characteristics): Updated/Changed the MAX value of the Conversion Range (CR) to "5.25" V .................................................................................................................... 115 • Table 7-26: Updated/Changed "(See Figure 76)" text to crossreference Figure 7-12, Differential Nonlinearity (DNL) Error ......................................................................................................................... 115 • Section 7.12.1 Corrected size of SPI baud rate generator, 11 bit, not 8 bit ............................................... 130 • Section 7.12.4 (MibSPI/SPI Master Mode I/O Timing Specifications): Updated/Changed MibSPI timings ............ 134 • Section 7.12.5 (SPI Slave Mode I/O Timings): Updated/Changed MibSPI timings ....................................... 138 • Section 8 (Applications, Implementation, and Layout): Added new section. ............................................... 142 • Section 9.1 (Development Support): Added new subsection ................................................................ 143 • Figure 9-1 (RM44Lx20 Device Numbering Conventions): Updated/Changed Die Revision ............................. 143 • Section 9.3.1 (Related Documentation from Texas Instruments): Added Silicon Errata Revision A references ...... 145 • Section 9.3.2 (Receiving Notification of Documentation Updates): Added subsection identifying the Product Folder "Alert me" button. .......................................................................................................... 145 • Section 9.7.1 (Device Identification Code Register): Added device identification code register value for silicon "Rev A" .............................................................................................................................. 147 • Section 9.8 (Module Certifications): Added missing subsections numbering. ............................................. 148 • Section 10.1 (Packaging Information): Updated/Changed paragraph ...................................................... 153 8 Revision History Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: RM44L920 RM44L520 |
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