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RM46L440 Datasheet(PDF) 5 Page - Texas Instruments |
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RM46L440 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 176 page RM46L440, RM46L840 www.ti.com SPNS183C – SEPTEMBER 2012 – REVISED JUNE 2015 Table of Contents 1 Device Overview ......................................... 1 6.10 Flash Memory ....................................... 79 1.1 Features .............................................. 1 6.11 Tightly Coupled RAM Interface Module ............. 82 1.2 Applications ........................................... 2 6.12 Parity Protection for Accesses to Peripheral RAMs 82 1.3 Description ............................................ 2 6.13 On-Chip SRAM Initialization and Testing ........... 84 1.4 Functional Block Diagram ............................ 4 6.14 External Memory Interface (EMIF) .................. 86 2 Revision History ......................................... 6 6.15 Vectored Interrupt Manager ......................... 94 3 Device Comparison ..................................... 7 6.16 DMA Controller ...................................... 98 4 Terminal Configuration and Functions ............. 8 6.17 Real Time Interrupt Module ........................ 100 4.1 PGE QFP Package Pinout (144-Pin) ................. 8 6.18 Error Signaling Module ............................. 102 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) .. 9 6.19 Reset / Abort / Error Sources ...................... 106 4.3 Terminal Functions ................................. 10 6.20 Digital Windowed Watchdog ....................... 109 5 Specifications .......................................... 42 6.21 Debug Subsystem ................................. 110 5.1 Absolute Maximum Ratings Over Operating Free- 7 Peripheral Information and Electrical Air Temperature Range ............................ 42 Specifications ......................................... 115 5.2 ESD Ratings ........................................ 42 7.1 Enhanced Translator PWM Modules (ePWM) ..... 115 5.3 Power-On Hours (POH) ............................. 42 7.2 Enhanced Capture Modules (eCAP) ............... 120 5.4 Device Recommended Operating Conditions ....... 43 7.3 Enhanced Quadrature Encoder (eQEP) ........... 122 5.5 Switching Characteristics Over Recommended 7.4 Multibuffered 12bit Analog-to-Digital Converter .... 123 Operating Conditions for Clock Domains ........... 44 7.5 General-Purpose Input/Output ..................... 135 5.6 Wait States Required ............................... 44 7.6 Enhanced High-End Timer (N2HET) .............. 136 5.7 Power Consumption Over Recommended 7.7 Controller Area Network (DCAN) .................. 140 Operating Conditions ................................ 45 7.8 Local Interconnect Network Interface (LIN) ........ 141 5.8 Input/Output Electrical Characteristics Over 7.9 Serial Communication Interface (SCI) ............. 142 Recommended Operating Conditions ............... 46 7.10 Inter-Integrated Circuit (I2C) ....................... 143 5.9 Thermal Resistance Characteristics ................ 46 7.11 Multibuffered / Standard Serial Peripheral 5.10 Output Buffer Drive Strengths ...................... 47 Interface ............................................ 146 5.11 Input Timings ........................................ 48 7.12 Ethernet Media Access Controller ................. 158 5.12 Output Timings ...................................... 48 8 Device and Documentation Support .............. 162 5.13 Low-EMI Output Buffers ............................ 50 8.1 Device and Development-Support Tool 6 System Information and Electrical Nomenclature ...................................... 162 Specifications ........................................... 51 8.2 Documentation Support ............................ 163 6.1 Device Power Domains ............................. 51 8.3 Trademarks ........................................ 163 6.2 Voltage Monitor Characteristics ..................... 51 8.4 Electrostatic Discharge Caution ................... 163 6.3 Power Sequencing and Power On Reset ........... 53 8.5 Glossary ............................................ 163 6.4 Warm Reset (nRST) ................................. 55 8.6 Device Identification ................................ 164 6.5 ARM Cortex-R4F CPU Information ................. 56 8.7 Module Certifications ............................... 166 6.6 Clocks ............................................... 59 9 Mechanical Packaging and Orderable 6.7 Clock Monitoring .................................... 68 Information ............................................. 171 6.8 Glitch Filters ......................................... 70 9.1 Packaging Information ............................. 171 6.9 Device Memory Map ................................ 71 Copyright © 2012–2015, Texas Instruments Incorporated Table of Contents 5 Submit Documentation Feedback Product Folder Links: RM46L440 RM46L840 |
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