SLE 66C640P

Short Product Information

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08.01

General Description

SLE 66C640P is another member of Infineon Technologies high-end security controller family in

advanced 0.22 µm CMOS technology. The CPU provides the high efficiency of the SAB 8051-

instruction set extended by additional powerful instructions together with enhanced performance,

memory sizes and security features. The internal clock frequency can be adjusted up to 10 MHz

independent of the clock rate of the terminal with the help of the PLL.

The controller IC offers 134 Kbytes of User-ROM, 256 bytes internal RAM, 4096 bytes XRAM and

64 Kbytes Slim-EEPROM. The Memory Management and Protection Unit allows a secure

separation of the operating system and the applications. Furthermore the MMU makes a secure

downloading of applications possible after the personalization of a card. These new features meet

the requirements of the next generation of multi application operating systems. For code

compatibility to the SLE 66CxxS family, a transparent mode for the MMU is available which allows

you to keep the memory mapping of the SLE 66CxxS products.

EEPROM

64 Kbyte

XRAM

4 Kbyte

ROM

136

Kbyte

UART

16-Bit CPU with

MMU

&

ECO 2000

Instruction Set

Voltage

Clock

Reset

Sleep Mode Logic

Sensors/Filters

Voltage Regulator

Address-/Data Bus

two

16-bit

Timer

Interrupt

CRC

RNG

PLL

Figure 2: Block Diagram SLE 66C640P

The CRC module allows the easy generation of checksums according to ISO/IEC 3309 (16-Bit-

CRC). To minimize the overall power consumption, the chip card controller IC offers a sleep mode.

The UART supports the half-duplex transmission protocols T=0 and T=1 according to ISO/IEC

7816-3. All relevant transmission parameters can be adjusted by software, as e.g. the clock

division factor, direct/inverse convention and the number of stop bits. Additionally, the I/O port can

be driven by communication routines realized in software.

The random number generator (RNG) is able to supply the CPU with true random numbers under

all conditions.

As an important measure, the chip provides a new and enhanced level of on-chip security features.