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DRV8301 Datasheet(PDF) 10 Page - Texas Instruments |
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DRV8301 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 39 page 10 DRV8301 SLOS719F – AUGUST 2011 – REVISED JANUARY 2016 www.ti.com Product Folder Links: DRV8301 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated 6.7 Buck Converter Characteristics TC = 25°C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VUVLO Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V ISD(PVDD2) Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 µA INON_SW(PVDD2) Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V 116 136 µA VEN_BUCK Enable threshold voltage No voltage hysteresis, rising and falling 1.11 1.25 1.36 V RDS_ON On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 m Ω ILIM Current limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A OTSD_BK Thermal shutdown 182 °C Fsw Switching frequency RT = 200 k Ω 450 581 720 kHz PWRGD VSENSE threshold VSENSE falling 92% VSENSE rising 94% VSENSE rising 109% VSENSE falling 107% Hysteresis VSENSE falling 2% Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω 6.8 SPI Timing Requirements (Slave Mode Only) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tSPI_READY SPI ready after EN_GATE transitions to HIGH PVDD > 6 V 5 10 ms tCLK Minimum SPI clock period 100 ns tCLKH Clock high time See Figure 1 40 tCLKL Clock low time See Figure 1 40 tSU_SDI SDI input data setup time 20 ns tHD_SDI SDI input data hold time 30 ns tD_SDO SDO output data delay time, CLK high to SDO valid CL = 20 pF 20 ns tHD_SDO SDO output data hold time See Figure 1 40 tSU_SCS SCS setup time See Figure 1 50 ns tHD_SCS SCS hold time 50 ns tHI_SCS SCS minimum high time before SCS active low 40 ns tACC SCS access time, SCS low to SDO out of high impedance 10 ns tDIS SCS disable time, SCS high to SDO high impedance 10 ns |
Similar Part No. - DRV8301_16 |
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Similar Description - DRV8301_16 |
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