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DRV8313PWP Datasheet(PDF) 4 Page - Texas Instruments |
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DRV8313PWP Datasheet(HTML) 4 Page - Texas Instruments |
4 / 37 page 4 DRV8313 SLVSBA5C – OCTOBER 2012 – REVISED NOVEMBER 2015 www.ti.com Product Folder Links: DRV8313 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Pin Functions (continued) PIN TYPE (1) DESCRIPTION NAME NO. PWP RHH nRESET 16 26 I Reset input. Active-low reset input initializes internal logic, clears faults, and disables the outputs, internal pulldown nSLEEP 17 27 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown OUT1 5 10 O Half-H bridge output, connect to the load OUT2 8 13 O Half-H bridge output, connect to the load OUT3 9 15 O Half-H bridge output, connect to the load PGND1 6 11 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors PGND2 7 12 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors PGND3 10 16 PWR Low-side FET source. Connect to GND or to low-side current-sense resistors V3P3 15 25 PWR Internal regulator. Internal supply voltage; bypass to GND with a 6.3 V, 0.47 µF ceramic capacitor; up to 10-mA external load VCP 3 7 PWR Charge pump. Connect a 16 V, 0.1 µF ceramic capacitor to VM VM 4, 11 9, 19 PWR Power supply. Connect to motor supply voltage; bypass to GND with two 0.1 µF (for each pin) plus one bulk capacitor rated for VM Thermal pad PWR Must be connected to ground (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT Power-supply voltage (VM) –0.3 65 V Power supply voltage ramp rate (VM) 0 2 V/µs Charge pump voltage (VCP, CPH) –0.3 VM + 12 V Charge pump negative switching pin (CPL) –0.3 VM V Internal regulator current output (V3P3) 0 10 mA Internal regulator voltage (V3P3) –0.3 3.8 V Control pin voltage (nRESET, nSLEEP, nFAULT, nCOMPO, ENx, INx) –0.5 7 V Comparator input-voltage (COMPP, COMPN) –0.5 7 V Open drain output current (nFAULT, nCOMPO) 0 10 mA Continuous phase node pin voltage (OUTx) –0.7 VM + 0.7 V Continuous 1/2-H-bridge source voltage (PGNDx) –600 600 mV Peak output current (OUTx) Internally limited A Operating junction temperature TJ –40 150 °C Storage temperature Tstg –60 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.2 ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±3000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1500 |
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